www.riscos.com Technical Support: The StrongARM Processor

Introduction to the StrongARM Revision 3, 04-Oct-96

FIQ usage is now deprecated. When you modify the FIQ vector, you will need to synchronise the code. The FIQ vector is often altered from IRQ or FIQ mode, but unfortunately OS_SynchroniseCodeAreas is not re-entrant, so cannot be used. For StrongARM compatibility we recommend you use the FIQ vector as follows:

     0000001C: LDR PC,&00000020
     00000020: 

and use the following code to do the synchronise manually when you write the instruction at location &1C (no synchronise is required when you alter the address at &20).

        .
        
        .
        MRC    CP15,0,R0,C0,C0           ; get processor ID
        AND    R0,R0,#&F000
        TEQ    R0,#&A000
        BNE    NotStrongARM
        MOV    R0,#&1C           
        MCR    CP15,0,R0,C7,C10,1        ; clean data cache entry for FIQ vector
        MOV    R0,#0
        MCR    CP15,0,R0,C7,C10,4        ; drain write buffer
        MCR    CP15,0,R0,C7,C5           ; flush whole instruction cache
  NotStrongARM
        .
        .
        .

If you want to write a complete FIQ handler into locations &1C to &FC, you should clean each 32-byte data cache line containing written code thus:

replace:

        MOV     R0,#&1C
        MCR     CP15,0,R0,C7,C10,1

with

        MOV     R0,#&E0              ; clean complete FIQ area
  01    MCR     CP15,0,R0,C7,C10,1   ; 32 bytes (1 cache line) at a time
        SUBS    R0,R0,#&20
        BGE     %BT01

This will usually be slower than the approach recommended above.

This is, of course, not a future-proof solution. We recommend that no new products use FIQ code. If you feel you have a pressing need to use FIQs, contact ART Developer Support for advice.

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